462 search results - page 37 / 93 » Parallel algorithm for hardware implementation of inverse ha... |
JCC
2010
13 years 5 months ago
2010
Abstract: Modern graphics processing units (GPUs) are flexibly programmable and have peak computational throughput significantly faster than conventional CPUs. Herein, we describ...
ICPR
2004
IEEE
14 years 8 months ago
2004
IEEE
Pattern recognition and computer vision tasks are computationally intensive, repetitive, and often exceed the capabilities of the CPU, leaving little time for higher level tasks. ...
EUROMICRO
2002
IEEE
14 years 10 days ago
2002
IEEE
The Mobile Multimedia Modem (M3)-DSP is based on a scalable, highly parallel DSP platform concept capable of delivering the processing power to create software solutions for tasks...
ASAP
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents a method, based on the formalism of affine recurrence equations, for the synthesis of digital circuits exploiting parallelism at the bit-level. In the initial ...
SIPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...