Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
In this paper, we present a strongly fault-tolerant design for the k-ary n-cube multiprocessor and examine its reconfigurability. Our design augments the k-ary n-cube with k j ...
We present a new analytical approach for the performance evaluation of asynchronous wormhole routing in k-ary n-cubes. Through the analysis of network flows, our methodology furni...
Bruno Ciciani, Claudio Paolucci, Michele Colajanni
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance g...
A network subsystem supporting a continuous media file system must guarantee a minimum throughput, a maximum delay, and a maximum jitter. We present a transport protocol that pro...
Darrell D. E. Long, Carol Osterbrock, Luis-Felipe ...