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HPCA
1997
IEEE
15 years 6 months ago
Design Issues and Tradeoffs for Write Buffers
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
Kevin Skadron, Douglas W. Clark
ICPP
1997
IEEE
15 years 6 months ago
Design of a Circuit-Switched Highly Fault-Tolerant k-ary n-cube
In this paper, we present a strongly fault-tolerant design for the k-ary n-cube multiprocessor and examine its reconfigurability. Our design augments the k-ary n-cube with k j ...
Baback A. Izadi, Füsun Özgüner
IPPS
1997
IEEE
15 years 6 months ago
An Accurate Model for the Performance Analysis of Deterministic Wormhole Routing
We present a new analytical approach for the performance evaluation of asynchronous wormhole routing in k-ary n-cubes. Through the analysis of network flows, our methodology furni...
Bruno Ciciani, Claudio Paolucci, Michele Colajanni
IPPS
1996
IEEE
15 years 6 months ago
A Memory Controller for Improved Performance of Streamed Computations on Symmetric Multiprocessors
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance g...
Sally A. McKee, William A. Wulf
ICDCS
1993
IEEE
15 years 6 months ago
Providing Performance Guarantees in an FDDI Network
A network subsystem supporting a continuous media file system must guarantee a minimum throughput, a maximum delay, and a maximum jitter. We present a transport protocol that pro...
Darrell D. E. Long, Carol Osterbrock, Luis-Felipe ...