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ACSC
2004
IEEE
13 years 11 months ago
Reducing Register Pressure Through LAER Algorithm
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
Gao Song
GECCO
2005
Springer
153views Optimization» more  GECCO 2005»
14 years 1 months ago
Evolving neural network ensembles for control problems
In neuroevolution, a genetic algorithm is used to evolve a neural network to perform a particular task. The standard approach is to evolve a population over a number of generation...
David Pardoe, Michael S. Ryoo, Risto Miikkulainen
LCPC
2005
Springer
14 years 1 months ago
Loop Selection for Thread-Level Speculation
Thread-level speculation (TLS) allows potentially dependent threads to speculatively execute in parallel, thus making it easier for the compiler to extract parallel threads. Howeve...
Shengyue Wang, Xiaoru Dai, Kiran Yellajyosula, Ant...
WOWMOM
2006
ACM
92views Multimedia» more  WOWMOM 2006»
14 years 1 months ago
Inter-Regional Messenger Scheduling in Delay Tolerant Mobile Networks
The evolution of wireless devices along with the increase in user mobility have created new challenges such as network partitioning and intermittent connectivity. These new challe...
Khaled A. Harras, Kevin C. Almeroth
ICMCS
2007
IEEE
182views Multimedia» more  ICMCS 2007»
14 years 1 months ago
Computer Vision on Multi-Core Processors: Articulated Body Tracking
The recent emergence of multi-core processors enables a new trend in the usage of computers. Computer vision applications, which require heavy computation and lots of bandwidth, u...
Trista Pei-chun Chen, Dmitry Budnikov, Christopher...