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» Parallel processing flow models on desktop hardware
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FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
14 years 2 months ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling
MEMOCODE
2007
IEEE
14 years 2 months ago
Scheduling as Rule Composition
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
Nirav Dave, Arvind, Michael Pellauer
HICSS
2009
IEEE
106views Biometrics» more  HICSS 2009»
14 years 3 months ago
A Radical Approach to Network-on-Chip Operating Systems
Operating systems were created to provide multiple tasks with access to scarce hardware resources like CPU, memory, or storage. Modern programmable hardware, however, may contain ...
Michael Engel, Olaf Spinczyk
ICDM
2010
IEEE
189views Data Mining» more  ICDM 2010»
13 years 6 months ago
S4: Distributed Stream Computing Platform
Abstract--S4 is a general-purpose, distributed, scalable, partially fault-tolerant, pluggable platform that allows programmers to easily develop applications for processing continu...
Leonardo Neumeyer, Bruce Robbins, Anish Nair, Anan...
SOCA
2010
IEEE
13 years 7 months ago
Short-term performance management by priority-based queueing
Service-based IT infrastructures serve many different business processes on a shared infrastructure in parallel. The automated request execution on the interconnected software com...
Christian Markl, Oliver Hühn, Martin Bichler