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» Parallel processing flow models on desktop hardware
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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 5 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
IPPS
2006
IEEE
14 years 1 months ago
High-performance computing in remotely sensed hyperspectral imaging: the Pixel Purity Index algorithm as a case study
The incorporation of last-generation sensors to airborne and satellite platforms is currently producing a nearly continual stream of high-dimensional data, and this explosion in t...
Antonio Plaza, David Valencia, Javier Plaza
TOMS
1998
148views more  TOMS 1998»
13 years 7 months ago
PELLPACK: A Problem-Solving Environment for PDE-Based Applications on Multicomputer Platforms
This paper presents the software architecture and implementation of the problem solving environment (PSE) PELLPACK for modeling physical objects described by partial differential ...
Elias N. Houstis, John R. Rice, Sanjiva Weerawaran...
CCGRID
2009
IEEE
14 years 2 months ago
Natively Supporting True One-Sided Communication in
As high-end computing systems continue to grow in scale, the performance that applications can achieve on such large scale systems depends heavily on their ability to avoid explic...
Gopalakrishnan Santhanaraman, Pavan Balaji, K. Gop...
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
14 years 1 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...