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» Parallel simulation of chip-multiprocessor architectures
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181
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INFOCOM
2002
IEEE
16 years 10 days ago
Ultrafast Photonic Label Switch for Asynchronous Packets of Variable Length
- This paper describes new optical switching architectures supporting asynchronous variable-length packets. Output line contention is resolved by optical delay line buffers. By int...
Masayuki Murata, Ken-ichi Kitayama
ICS
2010
Tsinghua U.
16 years 6 days ago
Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization
We explore the intersection between an emerging class of architectures and a prominent workload: GPGPUs (General-Purpose Graphics Processing Units) and regular expression matching...
Jamin Naghmouchi, Daniele Paolo Scarpazza, Mladen ...
203
Voted
ISCA
1994
IEEE
123views Hardware» more  ISCA 1994»
15 years 11 months ago
Software-Extended Coherent Shared Memory: Performance and Cost
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
David Chaiken, Anant Agarwal
DAC
2005
ACM
15 years 9 months ago
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips
Microfluidic biochips promise to revolutionize biosensing and clinical diagnostics. As more bioassays are executed concurrently on a biochip, system integration and design complex...
Fei Su, Krishnendu Chakrabarty
169
Voted
JUCS
2006
95views more  JUCS 2006»
15 years 7 months ago
Fault Tolerant Neural Predictors for Compression of Sensor Telemetry Data
: When dealing with remote systems, it is desirable that these systems are capable of operation within acceptable levels with minimal control and maintenance. In terms or transmiss...
Rajasvaran Logeswaran