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» Parallel simulation of chip-multiprocessor architectures
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ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
14 years 19 days ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
SIGGRAPH
1994
ACM
14 years 15 days ago
IRIS performer: a high performance multiprocessing toolkit for real-time 3D graphics
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
John Rohlf, James Helman
HYBRID
2000
Springer
14 years 1 days ago
Modular Specification of Hybrid Systems in CHARON
Abstract. We propose a language, called Charon, for modular specification of interacting hybrid systems. For hierarchical description of the system architecture, Charon supports bu...
Rajeev Alur, Radu Grosu, Yerang Hur, Vijay Kumar, ...
FTCS
1993
123views more  FTCS 1993»
13 years 9 months ago
Fast, On-Line Failure Recovery in Redundant Disk Arrays
This paper describes and evaluates two algorithms for performing on-line failure recovery (data reconstruction) in redundant disk arrays. It presents an implementation of disk-ori...
Mark Holland, Garth A. Gibson, Daniel P. Siewiorek
TROB
2002
112views more  TROB 2002»
13 years 8 months ago
SHaDe, a new 3-DOF haptic device
This paper presents a new type of haptic device using spherical geometry. The basic idea of haptic devices is to provide users with feedback information on the motion and/or force ...
Lionel Birglen, Clément Gosselin, Nicolas P...