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» Parallel simulation of chip-multiprocessor architectures
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INFOCOM
2003
IEEE
14 years 3 months ago
Exploiting Parallelism to Boost Data-Path Rate in High-Speed IP/MPLS Networking
Abstract—Link bundling is a way to increase routing scalability whenever a pair of Label Switching Routers in MPLS are connected by multiple parallel links. However, link bundlin...
Indra Widjaja, Anwar Elwalid
ICPP
2000
IEEE
14 years 2 months ago
Issues in Designing and Implementing a Scalable Virtual Interface Architecture
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
Shailabh Nagar, Anand Sivasubramaniam, Jorge Rodri...
ISORC
2002
IEEE
14 years 2 months ago
ARTISST: An Extensible and Modular Simulation Tool for Real-Time Systems
ARTISST (ARTISST is a Real-Time System Simulation Tool) is a modular event-driven simulation framework for real-time systems. It is targeted towards the performance evaluation of ...
David Decotigny, Isabelle Puaut
GPC
2009
Springer
13 years 7 months ago
I/O Device Virtualization in the Multi-core era, a QoS Perspective
In this paper, we propose an extension to the I/O device architecture, as recommended in the PCI-SIG IOV specification, for virtualizing network I/O devices. The aim is to enable ...
J. Lakshmi, S. K. Nandy
IPPS
2007
IEEE
14 years 4 months ago
A Framework for Modeling Operating System Mechanisms in the Simulation of Network Protocols for Real-Time Distributed Systems
In this paper we present a software tool for the simulation of distributed real-time embedded systems. Our tool is based on the popular NS-2 package for simulating the networking ...
Paolo Pagano, Prashant Batra, Giuseppe Lipari