Sciweavers

1016 search results - page 106 / 204
» Parallelism Constraints
Sort
View
IEEEPACT
2002
IEEE
14 years 1 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
DEBS
2011
ACM
13 years 14 days ago
Declarative data-driven coordination
Many data-driven social and Web applications involve collaboration and coordination. The vision of declarative data-driven coordination (D3C), proposed in [9], is to support coord...
Johannes Gehrke
HCI
2007
13 years 10 months ago
ParSketch: A Sketch-Based Interface for a 2D Parametric Geometry Editor
ParSketch is a software prototype to evaluate the usability and functionality of a sketching interface aimed at defining 2D parametric sections. Currently, ParSketch interprets str...
Ferran Naya, Manuel Contero, Nuria Aleixos, Pedro ...
SP
2008
IEEE
159views Security Privacy» more  SP 2008»
13 years 8 months ago
Inferring neuronal network connectivity from spike data: A temporal data mining approach
Abstract. Understanding the functioning of a neural system in terms of its underlying circuitry is an important problem in neuroscience. Recent developments in electrophysiology an...
Debprakash Patnaik, P. S. Sastry, K. P. Unnikrishn...
PPOPP
2009
ACM
14 years 9 months ago
Safe open-nested transactions through ownership
Researchers in transactional memory (TM) have proposed open nesting as a methodology for increasing the concurrency of transactional programs. The idea is to ignore "low-leve...
Kunal Agrawal, I.-Ting Angelina Lee, Jim Sukha