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FCCM
2009
IEEE
171views VLSI» more  FCCM 2009»
14 years 2 months ago
Accelerating SPICE Model-Evaluation using FPGAs
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
Nachiket Kapre, André DeHon
ICPPW
2009
IEEE
14 years 2 months ago
Hardware Microkernels for Heterogeneous Manycore Systems
Abstract— The migration away from power-hungry, speculative execution procesors towards manycore architectures is good news for the embedded and real-time systems community. Comm...
Jason Agron, David L. Andrews
IPPS
2007
IEEE
14 years 1 months ago
A Survey of Worst-Case Execution Time Analysis for Real-Time Java
As real-time systems become more prevalent, there is a need to guarantee that these increasingly complex systems perform as designed. One technique involves a static analysis to p...
Trevor Harmon, Raymond Klefstad
HIPC
2007
Springer
14 years 1 months ago
qTLB: Looking Inside the Look-Aside Buffer
Rapid evolution of multi-core platforms is putting additional stress on shared processor resources like TLB. TLBs have mostly been private resources for the application running on ...
Omesh Tickoo, Hari Kannan, Vineet Chadha, Ramesh I...
IPPS
2006
IEEE
14 years 1 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...