1074 search results - page 143 / 215 » Parallelizing post-placement timing optimization |
ISCAPDCS
2004
13 years 11 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
JNW
2008
13 years 10 months ago
2008
Recently overlay networks have emerged as an efficient and flexible method for content distribution. An overlay network is a network running on top of another network, usually the ...
CJ
1999
13 years 9 months ago
1999
We present a compiler optimization approach that uses the simulated evolution (SE) paradigm to enhance the finish time of heuristically scheduled computations with communication t...
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
Battery lifetime, a primary design constraint for mobile embedded systems, has been shown to depend heavily on the load current profile. This paper explores how scheduling guidel...
CCGRID
2006
IEEE
14 years 4 months ago
2006
IEEE
Simulation and optimization of complex mechanical and electronical systems is a very time consuming and computationally intensive task. Therefore, metamodeling techniques are ofte...