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ISCAPDCS
2004
13 years 10 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
CCGRID
2010
IEEE
13 years 10 months ago
An MPI-Stream Hybrid Programming Model for Computational Clusters
The MPI programming model hides network type and topology from developers, but also allows them to seamlessly distribute a computational job across multiple cores in both an intra ...
Emilio Pasquale Mancini, Gregory Marsh, Dhabaleswa...
HPDC
2010
IEEE
13 years 9 months ago
Reshaping text data for efficient processing on Amazon EC2
Text analysis tools are nowadays required to process increasingly large corpora which are often organized as small files (abstracts, news articles, etc). Cloud computing offers a ...
Gabriela Turcu, Ian T. Foster, Svetlozar Nestorov
BMCBI
2010
116views more  BMCBI 2010»
13 years 8 months ago
permGPU: Using graphics processing units in RNA microarray association studies
Background: Many analyses of microarray association studies involve permutation, bootstrap resampling and crossvalidation, that are ideally formulated as embarrassingly parallel c...
Ivo D. Shterev, Sin-Ho Jung, Stephen L. George, Ko...
BMCBI
2008
115views more  BMCBI 2008»
13 years 8 months ago
BioGraphE: high-performance bionetwork analysis using the Biological Graph Environment
Background: Graphs and networks are common analysis representations for biological systems. Many traditional graph algorithms such as k-clique, k-coloring, and subgraph matching h...
George Chin Jr., Daniel G. Chavarría-Mirand...
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