71 search results - page 4 / 15 » Parameterized Function Evaluation for FPGAs |
FPL
2005
Springer
14 years 3 months ago
2005
Springer
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
MSE
2005
IEEE
14 years 3 months ago
2005
IEEE
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short co...
FCCM
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
ISVC
2009
Springer
14 years 4 months ago
2009
Springer
Image segmentation techniques are predominately based on parameter-laden optimization processes. The segmentation objective function traditionally involves parameters (i.e. weights...
FPGA
2007
ACM
14 years 4 months ago
2007
ACM
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...