149 search results - page 19 / 30 » Parametric Fault Simulation and Test Vector Generation |
DDECS
2006
IEEE
14 years 1 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
ECBS
2011
IEEE
12 years 7 months ago
2011
IEEE
Abstract—Software systems are typically large and exhaustive testing of all possible input parameters is usually not feasible. Testers select tests that they anticipate may catch...
ISSRE
2007
IEEE
13 years 9 months ago
2007
IEEE
During development and testing, changes made to a system to repair a detected fault can often inject a new fault into the code base. These injected faults may not be in the same f...
EVOW
2008
Springer
13 years 9 months ago
2008
Springer
Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodolo...
ET
2000
13 years 7 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...