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» Part III: routers with very small buffers
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ICC
2007
IEEE
138views Communications» more  ICC 2007»
14 years 5 months ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi
ICC
2007
IEEE
163views Communications» more  ICC 2007»
14 years 5 months ago
Packet Dispatching Algorithms with the Static Connection Patterns Scheme for Three-Stage Buffered Clos-Network Switches
—Rapid expansion of the Internet and increasing demand for multimedia services fosters an immediate need for the development of new high-capacity networks capable of supporting t...
Janusz Kleban, Hugo Santos
INFOCOM
2006
IEEE
14 years 4 months ago
Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics
— Three-stage non-blocking switching fabrics are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Congestion (output contention) man...
Nikolaos Chrysos, Manolis Katevenis
VLDB
1987
ACM
90views Database» more  VLDB 1987»
14 years 2 months ago
Index Access with a Finite Buffer
: A buffer is a main-memory area used to reduce accessto disks. The buffer holds pages from secondary storage files. A processrequesting a page causesa fault if the pageis not in t...
Giovanni Maria Sacco
CF
2008
ACM
14 years 26 days ago
Multi-terabit ip lookup using parallel bidirectional pipelines
To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi...
Weirong Jiang, Viktor K. Prasanna