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» Partial Behavioural Models for Requirements and Early Design
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WSC
1998
13 years 9 months ago
Warehouse Design through Dynamic Simulation
Intel's new processors in mid-1997 were a dramatic increased in speed and size over their ancestors. The increased size caused box volume to increase beyond the capacity of t...
Mark Kosfeld
IPPS
2009
IEEE
14 years 3 months ago
High-level estimation and trade-off analysis for adaptive real-time systems
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrho...
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
14 years 2 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
IPPS
2006
IEEE
14 years 2 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
IJES
2008
83views more  IJES 2008»
13 years 8 months ago
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures
Reconfigurable ALU Array (RAA) architectures--representing a popular class of Coarse-grained Reconfigurable Architectures--are gaining in popularity especially for media applicati...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt