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CSSE
2008
IEEE
14 years 4 months ago
Generation of Executable Representation for Processor Simulation with Dynamic Translation
Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive...
Jiajia Song, HongWei Hao, Claude Helmstetter, Vani...
APLAS
2005
ACM
14 years 4 months ago
Race Conditions in Message Sequence Charts
Message Sequence Charts (MSCs) are a graphical language for the description of scenarios in terms of message exchanges between communicating components in a distributed environment...
Chien-An Chen, Sara Kalvala, Jane Sinclair
FMSD
2002
128views more  FMSD 2002»
13 years 10 months ago
Combining Software and Hardware Verification Techniques
Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of reali...
Robert P. Kurshan, Vladimir Levin, Marius Minea, D...
ORDER
2010
110views more  ORDER 2010»
13 years 8 months ago
The Complexity of Embedding Orders into Small Products of Chains
Embedding a partially ordered set into a product of chains is a classical way to encode it. Such encodings have been used in various fields such as object oriented programming or ...
Olivier Raynaud, Eric Thierry
CSFW
2011
IEEE
12 years 10 months ago
The Complexity of Quantitative Information Flow Problems
—In this paper, we investigate the computational complexity of quantitative information flow (QIF) problems. Information-theoretic quantitative relaxations of noninterference (b...
Pavol Cerný, Krishnendu Chatterjee, Thomas ...