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FPL
2000
Springer
128views Hardware» more  FPL 2000»
13 years 11 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
PODS
1991
ACM
131views Database» more  PODS 1991»
13 years 11 months ago
Termination Detection in Logic Programs using Argument Sizes
d Abstract Kirack Sohn and Allen Van Gelder University of California, Santa Cruz Progress on automated termination detection for logic programs is reported. The prospects for han...
Kirack Sohn, Allen Van Gelder
CORR
2010
Springer
137views Education» more  CORR 2010»
13 years 7 months ago
Verification of Java Bytecode using Analysis and Transformation of Logic Programs
State of the art analyzers in the Logic Programming (LP) paradigm are nowadays mature and sophisticated. They allow inferring a wide variety of global properties including terminat...
Elvira Albert, Miguel Gómez-Zamalloa, Laure...
INAP
2001
Springer
14 years 4 days ago
Defeasible Logic
We often reach conclusions partially on the basis that we do not have evidence that the conclusion is false. A newspaper story warning that the local water supply has been contamin...
Donald Nute
ICDAR
2007
IEEE
13 years 9 months ago
Example-Based Logical Labeling of Document Title Page Images
This paper presents a flexible and effective examplebased approach for labeling title pages which can be used for automated extraction of bibliographic data. The labels of intere...
Joost van Beusekom, Daniel Keysers, Faisal Shafait...