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IAJIT
2010
84views more  IAJIT 2010»
13 years 6 months ago
A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs
: A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate arra...
Bashar Al-Khalifa
POPL
2002
ACM
14 years 8 months ago
Towards automatic construction of staged compilers
Some compilation systems, such as offline partial evaluators and selective dynamic compilation systems, support staged optimizations. A staged optimization is one where a logicall...
Matthai Philipose, Craig Chambers, Susan J. Eggers
TLCA
2007
Springer
14 years 1 months ago
Computation by Prophecy
We describe a new method to represent (partial) recursive functions in type theory. For every recursive definition, we define a co-inductive type of prophecies that characterises...
Ana Bove, Venanzio Capretta
AAAI
2006
13 years 9 months ago
Fast SAT-based Answer Set Solver
Recent research shows that SAT (propositional satisfiability) techniques can be employed to build efficient systems to compute answer sets for logic programs. ASSAT and CMODELS ar...
Zhijun Lin, Yuanlin Zhang, Hector Hernandez
PPDP
2009
Springer
14 years 2 months ago
Relational semantics for effect-based program transformations: higher-order store
We give a denotational semantics to a type and effect system tracking reading and writing to global variables holding values that may include higher-order effectful functions. Re...
Nick Benton, Andrew Kennedy, Lennart Beringer, Mar...