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» Partitioning of VLSI Circuits and Systems
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ISQED
2000
IEEE
131views Hardware» more  ISQED 2000»
13 years 11 months ago
Low Power Testing of VLSI Circuits: Problems and Solutions
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
Patrick Girard
PDP
2003
IEEE
14 years 20 days ago
A Parallel Evolutionary Algorithm for Circuit Partitioning
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
Raul Baños, Consolación Gil, Maria D...
ARVLSI
1997
IEEE
96views VLSI» more  ARVLSI 1997»
13 years 11 months ago
Circuits and Microarchitecture for Gigahertz VLSI Designs
IBM founded the Austin Research Laboratory to investigate high-performance microprocessorbased systems. Initial e orts have focused on design for high frequency. This resulted in ...
Kevin J. Nowka, H. Peter Hofstee
FPL
2001
Springer
130views Hardware» more  FPL 2001»
13 years 12 months ago
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its eff...
Pierluigi Civera, Luca Macchiarulo, Maurizio Rebau...
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 11 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko