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CAV
2007
Springer
86views Hardware» more  CAV 2007»
14 years 3 months ago
From Liveness to Promptness
Liveness temporal properties state that something “good” eventually happens, e.g., every request is eventually granted. In Linear Temporal Logic (LTL), there is no a priori bo...
Orna Kupferman, Nir Piterman, Moshe Y. Vardi
HASE
2007
IEEE
14 years 21 days ago
Validation Support for Distributed Real-Time Embedded Systems in VDM++
We present a tool-supported approach to the validation of system-level timing properties in formal models of distributed real-time embedded systems. Our aim is to provide system a...
John S. Fitzgerald, Simon Tjell, Peter Gorm Larsen...
FORTE
2004
13 years 10 months ago
Localizing Program Errors for Cimple Debugging
Abstract. We present automated techniques for the explanation of counterexamples, where a counter-example should be understood as a sequence of program statements. Our approach is ...
Samik Basu, Diptikalyan Saha, Scott A. Smolka
DLOG
2006
13 years 10 months ago
Model checking the basic modalities of CTL with Description Logic
Abstract. Model checking is a fully automated technique for determining whether the behaviour of a finite-state reactive system satisfies a temporal logic specification. Despite th...
Shoham Ben-David, Richard J. Trefler, Grant E. Wed...
CONCUR
2001
Springer
14 years 1 months ago
Bounded Reachability Checking with Process Semantics
Bounded model checking has been recently introduced as an efficient verification method for reactive systems. In this work we apply bounded model checking to asynchronous systems....
Keijo Heljanko