472 search results - page 37 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
ASPLOS
1987
ACM
13 years 11 months ago
1987
ACM
One potentialdisadvantage of a machine with a reduced instruction. set is that object programs may be substantially larger than those for a machine with a richer, more complex ins...
CASES
2001
ACM
13 years 11 months ago
2001
ACM
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
Both inherently sequential code and limitations of analysis techniques prevent full parallelization of many applications by parallelizing compilers. Amdahl's Law tells us tha...
SIGMETRICS
1992
ACM
13 years 11 months ago
1992
ACM
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...