472 search results - page 56 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
EUROSYS
2007
ACM
14 years 5 months ago
2007
ACM
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
ICS
2005
Tsinghua U.
14 years 2 months ago
2005
Tsinghua U.
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
HPCA
1998
IEEE
14 years 1 months ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
CASES
2007
ACM
14 years 22 days ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...