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» Performance Evaluation of Memory Caches in Multiprocessors
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ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 1 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
VLDB
2005
ACM
121views Database» more  VLDB 2005»
14 years 2 months ago
Improving Database Performance on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...
Jingren Zhou, John Cieslewicz, Kenneth A. Ross, Mi...
ICDCS
1997
IEEE
14 years 28 days ago
Multi-threading and Remote Latency in Software DSMs
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
Kritchalach Thitikamol, Peter J. Keleher
RTCSA
2008
IEEE
14 years 3 months ago
Power-Aware Data Buffer Cache Management in Real-Time Embedded Databases
The demand for real-time data services in embedded systems is increasing. In these new computing platforms, using traditional buffer management schemes, whose goal is to minimize ...
Woochul Kang, Sang Hyuk Son, John A. Stankovic
DAC
2006
ACM
13 years 10 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...