472 search results - page 62 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
IPPS
1999
IEEE
14 years 1 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
TC
2011
13 years 3 months ago
2011
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
SIGCOMM
1995
ACM
14 years 8 days ago
1995
ACM
Integrated Layer Processing (ILP) is an implementation concept which "permit[s] the implementor the option of performing all the [data] manipulation steps in one or two integ...
ICPP
1999
IEEE
14 years 1 months ago
1999
IEEE
Task graph scheduling has been found effective in performance prediction and optimization of parallel applications. A number of static scheduling algorithms have been proposed for...
RTAS
2010
IEEE
13 years 7 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...