114 search results - page 11 / 23 » Performance Evaluation of Task Pools Based on Hardware Synch... |
IEEEPACT
2007
IEEE
14 years 2 months ago
2007
IEEE
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
TASE
2008
IEEE
13 years 7 months ago
2008
IEEE
This paper considers a matrix-based discrete event control approach for a warehouse. The control system is organized in two modules: a dynamic model and a controller. The model pro...
CJ
1999
13 years 7 months ago
1999
We present a compiler optimization approach that uses the simulated evolution (SE) paradigm to enhance the finish time of heuristically scheduled computations with communication t...
SP
1997
IEEE
13 years 12 months ago
1997
IEEE
This paper analyzes a network-baseddenial of service attack for IP (Internet Protocol) based networks. It is popularly called SYN flooding. It works by an attacker sending many T...