Sciweavers

114 search results - page 5 / 23
» Performance Evaluation of Task Pools Based on Hardware Synch...
Sort
View
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
14 years 28 days ago
Efficient symbol synchronization techniques using variable FIR or IIR interpolation filters
Maximum Likelihood estimation theory can be used to develop optimal timing recovery schemes for digital communication systems. Tunable digital interpolation filters are commonly ...
Martin Makundi, Timo I. Laakso
CF
2010
ACM
14 years 23 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
ICASSP
2011
IEEE
12 years 11 months ago
Score fusion and calibration in multiple language detectors with large performance variation
In a large-scale language detection task, performance variation found between different component systems and different target languages has an adverse effect to the pooled error ...
Raymond W. M. Ng, Cheung-Chi Leung, Tan Lee, Bin M...
SC
1995
ACM
13 years 11 months ago
Lazy Release Consistency for Hardware-Coherent Multiprocessors
Release consistency is a widely accepted memory model for distributed shared memory systems. Eager release consistency represents the state of the art in release consistent protoc...
Leonidas I. Kontothanassis, Michael L. Scott, Rica...
ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
13 years 11 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...