Sciweavers

891 search results - page 140 / 179
» Performance Issues in Parallelized Network Protocols
Sort
View
IEEEPACT
2008
IEEE
14 years 2 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
PADS
2004
ACM
14 years 1 months ago
The Effect of Detail on Ethernet Simulation
An important question for network simulation is what level of detail is required to obtain a desired level of accuracy. While in some networks, the level of detail is an open rese...
Alefiya Hussain, Aman Kapoor, John S. Heidemann
CN
2007
99views more  CN 2007»
13 years 8 months ago
Design and implementation of a secure wide-area object middleware
Wide-area service replication is becoming increasingly common, with the emergence of new operational models such as content delivery networks and computational grids. This paper d...
Bogdan C. Popescu, Bruno Crispo, Andrew S. Tanenba...
TPDS
1998
129views more  TPDS 1998»
13 years 8 months ago
The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics
—Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconn...
W. Stephen Lacy, José Cruz-Rivera, D. Scott...
PODC
2012
ACM
11 years 11 months ago
On the (limited) power of non-equivocation
In recent years, there have been a few proposals to add a small amount of trusted hardware at each replica in a Byzantine fault tolerant system to cut back replication factors. Th...
Allen Clement, Flavio Junqueira, Aniket Kate, Rodr...