481 search results - page 60 / 97 » Performance Modeling and Measurement of Parallelized Code fo... |
ICA3PP
2005
Springer
14 years 2 months ago
2005
Springer
Shared Memory is an interesting communication paradigm for SMP machines and clusters. Weak consistency models have been proposed to improve efficiency of shared memory applications...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ICPP
1994
IEEE
14 years 28 days ago
1994
IEEE
Shared memory in a parallel computer provides prowith the valuable abstraction of a shared address space--through which any part of a computation can access any datum. Although un...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Due to shared cache contentions and interconnect delays, data prefetching is more critical in alleviating penalties from increasing memory latencies and demands on Chip-Multiproce...