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CHI
2010
ACM
15 years 11 months ago
Predicting the cost of error correction in character-based text entry technologies
Researchers have developed many models to predict and understand human performance in text entry. Most of the models are specific to a technology or fail to account for human fact...
Ahmed Sabbir Arif, Wolfgang Stuerzlinger
HPCA
2009
IEEE
16 years 5 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
MOBISYS
2009
ACM
16 years 5 months ago
Predictive methods for improved vehicular WiFi access
With the proliferation of WiFi technology, many WiFi networks are accessible from vehicles on the road making vehicular WiFi access realistic. However, several challenges exist: l...
Pralhad Deshpande, Anand Kashyap, Chul Sung, Samir...
SLIP
2009
ACM
15 years 11 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
ICS
2009
Tsinghua U.
15 years 11 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron