260 search results - page 17 / 52 » Performance Modelling and Optimization of Memory Access on C... |
WMPI
2004
ACM
14 years 29 days ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
PROPERTYTESTING
2010
13 years 5 months ago
2010
We initiate the study of sublinear-time algorithms in the external memory model [Vit01]. In this model, the data is stored in blocks of a certain size B, and the algorithm is char...
SPAA
1996
ACM
13 years 11 months ago
1996
ACM
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
WMPI
2004
ACM
14 years 29 days ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...