260 search results - page 23 / 52 » Performance Modelling and Optimization of Memory Access on C... |
PPOPP
2010
ACM
14 years 4 months ago
2010
ACM
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
EUROPAR
1997
Springer
13 years 11 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
IPPS
1997
IEEE
13 years 11 months ago
1997
IEEE
We present the Data Parallel Fortran (DPF) benchmark suite, a set of data parallel Fortran codes forevaluatingdata parallel compilers appropriatefor any target parallel architectu...
PC
2010
13 years 6 months ago
2010
Compute unified device architecture (CUDA) is a software development platform that allows us to run C-like programs on the nVIDIA graphics processing unit (GPU). This paper prese...