This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
In this article we present the design choices and the evaluation of a batch scheduler for large clusters, named OAR. This batch scheduler is based upon an original design that emp...
Nicolas Capit, Georges Da Costa, Yiannis Georgiou,...
In a recent work, we have shown that it is not possible to dependably build any type of distributed f fault or intrusiontolerant system under the asynchronous model. This result f...
Paulo Sousa, Nuno Ferreira Neves, Paulo Verí...
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
Sailesh Kumar, Jonathan S. Turner, Patrick Crowley