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ICS
2003
Tsinghua U.
14 years 1 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
NSDI
2004
13 years 9 months ago
Designing a DHT for Low Latency and High Throughput
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
Frank Dabek, Jinyang Li, Emil Sit, James Robertson...
SAC
2004
ACM
14 years 1 months ago
GD-GhOST: a goal-oriented self-tuning caching algorithm
A popular solution to internet performance problems is the widespread caching of data. Many caching algorithms have been proposed in the literature, most attempting to optimize fo...
Ganesh Santhanakrishnan, Ahmed Amer, Panos K. Chry...
JSSPP
2004
Springer
14 years 1 months ago
Enhancements to the Decision Process of the Self-Tuning dynP Scheduler
The self-tuning dynP scheduler for modern cluster resource management systems switches between different basic scheduling policies dynamically during run time. This allows to reac...
Achim Streit
TSE
1998
116views more  TSE 1998»
13 years 7 months ago
A Framework-Based Approach to the Development of Network-Aware Applications
— Modern networks provide a QoS (quality of service) model to go beyond best-effort services, but current QoS models are oriented towards low-level network parameters (e.g., band...
Jürg Bolliger, Thomas R. Gross