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» Performance analysis of a user-level memory server
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IPPS
2007
IEEE
14 years 1 months ago
A Comprehensive Analysis of OpenMP Applications on Dual-Core Intel Xeon SMPs
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
Ryan E. Grant, Ahmad Afsahi
ICS
2009
Tsinghua U.
14 years 2 months ago
QuakeTM: parallelizing a complex sequential application using transactional memory
“Is transactional memory useful?” is the question that cannot be answered until we provide substantial applications that can evaluate its capabilities. While existing TM appli...
Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal...
ICNS
2009
IEEE
14 years 2 months ago
Analysis and Experimental Evaluation of Data Plane Virtualization with Xen
Combining end-host, server and router virtualization could offer isolated and malleable virtual networks of different types, owners and protocols, all sharing one physical infrast...
Fabienne Anhalt, Pascale Vicat-Blanc Primet
SIGMETRICS
2003
ACM
199views Hardware» more  SIGMETRICS 2003»
14 years 19 days ago
Data cache locking for higher program predictability
Caches have become increasingly important with the widening gap between main memory and processor speeds. However, they are a source of unpredictability due to their characteristi...
Xavier Vera, Björn Lisper, Jingling Xue
ASPLOS
2012
ACM
12 years 3 months ago
Comprehensive kernel instrumentation via dynamic binary translation
Dynamic binary translation (DBT) is a powerful technique that enables fine-grained monitoring and manipulation of an existing program binary. At the user level, it has been emplo...
Peter Feiner, Angela Demke Brown, Ashvin Goel