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EMSOFT
2004
Springer
14 years 28 days ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
CN
2002
77views more  CN 2002»
13 years 7 months ago
Architecture of a Web server accelerator
We describe the design, implementation and performance of a high-performance Web server accelerator which runs on an embedded operating system and improves Web server performance ...
Junehwa Song, Arun Iyengar, Eric Levy-Abegnoli, Da...
PLDI
2000
ACM
13 years 12 months ago
Caching function calls using precise dependencies
This paper describes the implementation of a purely functional programming language for building software systems. In this language, external tools like compilers and linkers are ...
Allan Heydon, Roy Levin, Yuan Yu
TC
2011
13 years 2 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
12 years 10 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross