— Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., u...
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
Data-shipping systems that allow inter-transaction caching raise the need of a transactional cache consistency maintenance (CCM) protocol because each client is able to cache a po...
Mobile Web pre-caching (Web prefetching and caching) is an explication of performance enhancement and storage limitation of mobile devices. In this paper, we present the granulari...
Data intensive service functions such as memory allocation/de-allocation, data prefetching, and data relocation can pollute processor cache in conventional systems since the same ...