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ISPASS
2010
IEEE
16 years 28 days ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
16 years 13 days ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson
RTSS
2007
IEEE
16 years 10 days ago
Chronos: Feedback Control of a Real Database System Performance
It is challenging to process transactions in a timely fashion using fresh data, e.g., current stock prices, since database workloads may considerably vary due to dynamic data/reso...
Kyoung-Don Kang, Jisu Oh, Sang Hyuk Son
IWDC
2001
Springer
140views Communications» more  IWDC 2001»
15 years 10 months ago
Satellite Systems Performance with TCP-IP Applications
Mobile Internet access is becoming extremely popular because users depend on the Internet for many activities in their daily routine. Satellites are well suited for mobile Interne...
Pierpaolo Loreti, Michele Luglio, Rohit Kapoor, J....
JPDC
2000
141views more  JPDC 2000»
15 years 5 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...