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» Performance of Hardware Compressed Main Memory
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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
13 years 8 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
14 years 2 months ago
A near optimal deblocking filter for H.264 advanced video coding
- We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant...
Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
ICPP
2009
IEEE
14 years 2 months ago
Perfomance Models for Blocked Sparse Matrix-Vector Multiplication Kernels
—Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architec...
Vasileios Karakasis, Georgios I. Goumas, Nectarios...
APCCAS
2006
IEEE
252views Hardware» more  APCCAS 2006»
13 years 10 months ago
A Display Order Oriented Scalable Video Decoder
As network technologies advance, Scalable Video Coding (SVC) has become increasingly popular due to its universal multimedia access capability and competitive compression performan...
Jia-Bin Huang, Yu-Kun Lin, Tian-Sheuan Chang
CCS
2011
ACM
12 years 8 months ago
VMCrypt: modular software architecture for scalable secure computation
Garbled circuits play a key role in secure computation. Unlike previous work, which focused mainly on efficiency and automation aspects of secure computation, in this paper we foc...
Lior Malka