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ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 16 days ago
Circuits for wide-window superscalar processors
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh...
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
14 years 2 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
IPPS
2000
IEEE
14 years 16 days ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
MSS
2007
IEEE
83views Hardware» more  MSS 2007»
14 years 2 months ago
The RAM Enhanced Disk Cache Project (REDCAP)
This paper presents the RAM Enhanced Disk Cache Project, REDCAP, a new cache of disk blocks which reduces the read I/O time by using a small portion of the main memory. The essent...
Pilar Gonzalez-Ferez, Juan Piernas, Toni Cortes
LCN
2006
IEEE
14 years 2 months ago
Efficient Packet Processing in User-Level OSes: A Study of UML
Network server consolidation has become popular through recent virtualization technology that builds secure, isolated network systems on shared hardware. One of the virtualization...
Younggyun Koh, Calton Pu, Sapan Bhatia, Charles Co...