955 search results - page 11 / 191 » Performance optimization of multiple memory architectures fo... |
PLDI
1995
ACM
13 years 11 months ago
1995
ACM
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, ge...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
JPDC
2008
13 years 7 months ago
2008
Energy saving is becoming one of the major design issues in processor architectures with multiple functional units (FUs). Nested loops are usually the most critical part in multim...
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...