955 search results - page 17 / 191 » Performance optimization of multiple memory architectures fo... |
CVPR
2007
IEEE
13 years 9 months ago
2007
IEEE
Considerable research work has been done in the area of surveillance and biometrics, where the goals have always been high performance, robustness in security and cost optimizatio...
CPHYSICS
2010
13 years 9 months ago
2010
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
In this paper we explore the impact of the block shape on blocked and vectorized versions of the Sparse Matrix-Vector Multiplication (SpMV) kernel and build upon previous work by ...
PLDI
2003
ACM
14 years 2 months ago
2003
ACM
As more complex DSP algorithms are realized in practice, an increasing need for high-level stream abstractions that can be compiled without sacrificing efficiency. Toward this en...
ARVLSI
1997
IEEE
14 years 17 days ago
1997
IEEE
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...