955 search results - page 39 / 191 » Performance optimization of multiple memory architectures fo... |
SC
2004
ACM
14 years 2 months ago
2004
ACM
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
ICPR
2004
IEEE
14 years 10 months ago
2004
IEEE
Pattern recognition and computer vision tasks are computationally intensive, repetitive, and often exceed the capabilities of the CPU, leaving little time for higher level tasks. ...
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
ASAP
2004
IEEE
14 years 24 days ago
2004
IEEE
Distributed local memories, or scratchpads, have been shown to effectively reduce cost and power consumption of application-specific accelerators while maintaining performance. Th...