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TVLSI
2008
120views more  TVLSI 2008»
13 years 9 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
PE
2007
Springer
97views Optimization» more  PE 2007»
13 years 9 months ago
On processor sharing and its applications to cellular data network provisioning
To develop simple traffic engineering rules for the downlink of a cellular system using Proportional Fairness (PF) scheduling, we study the “strict” and “approximate” ins...
Yujing Wu, Carey L. Williamson, Jingxiang Luo
JPDC
2010
137views more  JPDC 2010»
13 years 8 months ago
Parallel exact inference on the Cell Broadband Engine processor
—We present the design and implementation of a parallel exact inference algorithm on the Cell Broadband Engine (Cell BE). Exact inference is a key problem in exploring probabilis...
Yinglong Xia, Viktor K. Prasanna
EMSOFT
2001
Springer
14 years 2 months ago
Compiler Optimizations for Adaptive EPIC Processors
Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting...
Krishna V. Palem, Surendranath Talla, Weng-Fai Won...
JVM
2004
103views Education» more  JVM 2004»
13 years 11 months ago
The Virtual Processor: Fast, Architecture-Neutral Dynamic Code Generation
Tools supporting dynamic code generation tend too be low-level (leaving much work to the client application) or too intimately related with the language/system in which they are u...
Ian Piumarta