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ICMCS
2007
IEEE
123views Multimedia» more  ICMCS 2007»
14 years 3 months ago
Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling
The H.264 decoder has a sequential, control intensive front end that makes it difficult to leverage the potential performance of emerging manycore processors. Preparsing is a fun...
Jike Chong, Nadathur Satish, Bryan C. Catanzaro, K...
IPPS
2007
IEEE
14 years 3 months ago
Microarchitectural Support for Speculative Register Renaming
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission ...
Jesús Alastruey, Teresa Monreal, Víc...
FPL
2005
Springer
111views Hardware» more  FPL 2005»
14 years 2 months ago
Mutable Codesign for Embedded Protocol Processing
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
Todd S. Sproull, Gordon J. Brebner, Christopher E....
EUROPAR
2004
Springer
14 years 2 months ago
Scheduling of MPI Applications: Self-co-scheduling
Scheduling parallel jobs has been an active investigation area. The scheduler has to deal with heterogeneous workloads and try to obtain throughputs and response times such that en...
Gladys Utrera, Julita Corbalán, Jesú...
HPCA
2000
IEEE
14 years 1 months ago
Dynamic Cluster Assignment Mechanisms
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...
Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonz&a...