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SP
1999
IEEE
125views Security Privacy» more  SP 1999»
14 years 29 days ago
A Multi-Threading Architecture for Multilevel Secure Transaction Processing
A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design ...
Haruna R. Isa, William R. Shockley, Cynthia E. Irv...
ICPP
1997
IEEE
14 years 27 days ago
Automatic Parallelization and Scheduling of Programs on Multiprocessors using CASCH
r The lack of a versatile software tool for parallel program development has been one of the major obstacles for exploiting the potential of high-performance architectures. In this...
Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu, Wei Shu
PARLE
1993
14 years 24 days ago
On the Performance of Parallel Join Processing in Shared Nothing Database Systems
: Parallel database systems aim at providing high throughput for OLTP transactions as well as short response times for complex and data-intensive queries. Shared nothing systems re...
Robert Marek, Erhard Rahm
SWAT
1992
Springer
111views Algorithms» more  SWAT 1992»
14 years 23 days ago
Retrieval of scattered information by EREW, CREW and CRCW PRAMs
The k-compaction problem arises when k out of n cells in an array are non-empty and the contents of these cells must be moved to the first k locations in the array. Parallel algori...
Faith E. Fich, Miroslaw Kowaluk, Krzysztof Lorys, ...
MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
14 years 7 days ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin