584 search results - page 68 / 117 » Perspectives on Transactional Memory |
EUROSYS
2007
ACM
14 years 4 months ago
2007
ACM
We present a memory-aware load balancing (MALB) technique to dispatch transactions to replicas in a replicated database. Our MALB algorithm exploits knowledge of the working sets ...
IPPS
2000
IEEE
14 years 14 hour ago
2000
IEEE
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
EUROPDS
1997
13 years 9 months ago
1997
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
RTSS
2007
IEEE
14 years 1 months ago
2007
IEEE
The integration phase of real-time COTS-based systems is often problematic because when multiple tasks run concurrently, the interference at the bus level between cache fetching a...
ACMMSP
2006
ACM
14 years 1 months ago
2006
ACM
We present an implementation and evaluation of atomicity (also known as software transactions) for a dialect of Java. Our implementation is fundamentally different from prior work...