The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
—We consider the problem of minimizing upper bounds and maximizing lower bounds on information rates of stationary and ergodic discrete-time channels with memory. The channels we...
Parastoo Sadeghi, Pascal O. Vontobel, Ramtin Shams
To address performance limitations and expand their applications range, emerging and mature display technologies rely on the design of novel display controllers. Under current mod...
David Antonio-Torres, Paul F. Newbury, Paul F. Lis...
Over the past decade, there has been a lot of work in developing middleware for integrating and automating enterprise business processes. Today, with the growth in e-commerce and ...
Existing concurrency control algorithms do not well conform to various environments, in the performance perspective. Each algorithm has some assumption on the conflict characteris...