Sciweavers

584 search results - page 76 / 117
» Perspectives on Transactional Memory
Sort
View
SC
1995
ACM
13 years 11 months ago
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
Umakishore Ramachandran, Gautam Shah, Anand Sivasu...
CORR
2007
Springer
144views Education» more  CORR 2007»
13 years 7 months ago
Optimization of Information Rate Upper and Lower Bounds for Channels with Memory
—We consider the problem of minimizing upper bounds and maximizing lower bounds on information rates of stationary and ergodic discrete-time channels with memory. The channels we...
Parastoo Sadeghi, Pascal O. Vontobel, Ramtin Shams
FDL
2005
IEEE
14 years 1 months ago
Executable Specification of Novel Display Controllers
To address performance limitations and expand their applications range, emerging and mature display technologies rely on the design of novel display controllers. Under current mod...
David Antonio-Torres, Paul F. Newbury, Paul F. Lis...
VLDB
2001
ACM
87views Database» more  VLDB 2001»
14 years 1 days ago
Business Process Coordination: State of the Art, Trends, and Open Issues
Over the past decade, there has been a lot of work in developing middleware for integrating and automating enterprise business processes. Today, with the growth in e-commerce and ...
Umeshwar Dayal, Meichun Hsu, Rivka Ladin
DEXAW
1997
IEEE
77views Database» more  DEXAW 1997»
13 years 11 months ago
A Per-object Based Hybrid Concurrency Control
Existing concurrency control algorithms do not well conform to various environments, in the performance perspective. Each algorithm has some assumption on the conflict characteris...
Tae-Young Kwak, Yoon-Joon Lee, Myoung-Ho Kim