1493 search results - page 172 / 299 » Petascale computing with accelerators |
IWANN
2007
Springer
14 years 4 months ago
2007
Springer
This paper presents configuration methods for an existing neuromorphic hardware and shows first experimental results. The utilized mixed-signal VLSI1 device implements a highly a...
ASAP
2006
IEEE
14 years 4 months ago
2006
IEEE
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
VRML
2006
ACM
14 years 4 months ago
2006
ACM
The availability of more powerful mobile devices, sometimes equipped with graphics accelerators, is making it easier to experiment with mobile 3D graphics. In this paper, we explo...
ASAP
2005
IEEE
14 years 4 months ago
2005
IEEE
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
FPL
2005
Springer
14 years 4 months ago
2005
Springer
Abstract. We propose CUSTARD — CUStomisable Threaded ARchitecture — a soft processor design space that combines support for multiple hardware threads and automatically generate...