301 search results - page 12 / 61 » Physical design techniques for optimizing RTA-induced variat... |
ISVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
System-level design techniques promise a way to lessen the productivity gap between fabrication and design. Unfortunately, these techniques have been slow to catch on, in part bec...
DAC
2009
ACM
14 years 3 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
DOLAP
2007
ACM
14 years 11 days ago
2007
ACM
In this paper, we deal with the problem of determining the best possible physical implementation of an ETL workflow, given its logical-level description and an appropriate cost mo...
CAINE
2003
13 years 9 months ago
2003
Scan based or Line Sweep methods are a traditional mechanism to traverse the physical layout, or artwork of a microchip. These traversals are incremental in nature. They typically...
ICCAD
2007
IEEE
14 years 5 months ago
2007
IEEE
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...